Add thumb2 IT permutations
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@ -13,7 +13,7 @@ exec 'syn match armv6Instr "\%(SH\?\|Q\|U[QH]\?\)\%(ADD16\|SUB16\|ADD8\|SUB8\|AS
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exec 'syn match armv6Instr "\%(USAD8\|USADA8\|SSAT\|SSAT16\|USAT\|USAT16\)' . armCond . '\>"'
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exec 'syn match armv6Instr "\%(USAD8\|USADA8\|SSAT\|SSAT16\|USAT\|USAT16\)' . armCond . '\>"'
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exec 'syn match armv6Instr "\%(MOVT\|MRA\|MAR\|ORN\|BFC\|BFI\|SBFX\|UBFX\)' . armCond . '\>"'
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exec 'syn match armv6Instr "\%(MOVT\|MOVW\|MRA\|MAR\|ORN\|BFC\|BFI\|SBFX\|UBFX\)' . armCond . '\>"'
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exec 'syn match armv6Instr "\%(PKHBT\|PKHTB\|SXTH\|SXTB16\|SXTB\|SXTAH\|SXTAB16\|SXTAB\|UXTH\|UXTB\|UXTB16\|UXTAH\|UXTAB16\|UXTAB\|RBIT\|REV\|REV16\|REVSH\|SEL\)' . armCond . '\>"'
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exec 'syn match armv6Instr "\%(PKHBT\|PKHTB\|SXTH\|SXTB16\|SXTB\|SXTAH\|SXTAB16\|SXTAB\|UXTH\|UXTB\|UXTB16\|UXTAH\|UXTAB16\|UXTAB\|RBIT\|REV\|REV16\|REVSH\|SEL\)' . armCond . '\>"'
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@ -22,7 +22,7 @@ exec 'syn match armv6Mul "\%(UMAAL\|SMUAD\|SMLAD\|SMLALD\|SMUSD\|SMLSD\|SMLSLD\|
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exec 'syn match armv6LDR "\%(LDREX[HBD]\)' . armCond . '\>"'
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exec 'syn match armv6LDR "\%(LDREX[HBD]\)' . armCond . '\>"'
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exec 'syn match armv6STR "\%(STREX[HBD]\|CLREX\)' . armCond . '\>"'
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exec 'syn match armv6STR "\%(STREX[HBD]\|CLREX\)' . armCond . '\>"'
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syn match armv6InstrNoCond "\%(IT\|CBN\?Z\|TBB\|TBH\|CPSID\|CPSIE\|CPS\|SETEND\|SRS\%(IA\|IB\|DA\|DB\)\|RFE\%(IA\|IB\|DA\|DB\)\)\>"
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syn match armv6InstrNoCond "\%(IT[TE]\{0,3\}\|CBN\?Z\|TBB\|TBH\|CPSID\|CPSIE\|CPS\|SETEND\|SRS\%(IA\|IB\|DA\|DB\)\|RFE\%(IA\|IB\|DA\|DB\)\)\>"
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syn keyword armv6InstrNoCond MRRC2 MCRR2
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syn keyword armv6InstrNoCond MRRC2 MCRR2
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exec 'syn match armv7Instr "\%(DBG\|DMB\|DSB\|ISB\|SEV\|WFE\|WFI\|YIELD\)' . armCond . '\>"'
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exec 'syn match armv7Instr "\%(DBG\|DMB\|DSB\|ISB\|SEV\|WFE\|WFI\|YIELD\)' . armCond . '\>"'
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@ -14,6 +14,7 @@ sub r14, 0b1110110-50
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0x1234567890AbCdEfG
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0x1234567890AbCdEfG
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0xfff-0b1101+0xebbe&40%76*(0x0f)0b11/0x1f[0b110]42<>0xff|0xaa.c
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0xfff-0b1101+0xebbe&40%76*(0x0f)0b11/0x1f[0b110]42<>0xff|0xaa.c
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1:
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1:
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movwcs r1,r7
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and R2,r3
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and R2,r3
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bic r3 , r4
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bic r3 , r4
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eor r4,r5
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eor r4,r5
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@ -39,6 +40,20 @@ fdivs
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vdiv
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vdiv
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vsqrt
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vsqrt
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it
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itt
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ittt
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itttt
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ittttt
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ite
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itet
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iteet
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iteeee
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ite
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itee
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ittee
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iteeet
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s30doesd32
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s30doesd32
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vadd.i8 d12, d16, d31
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vadd.i8 d12, d16, d31
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