diff --git a/syntax/include/armv6_base_syntax.vim b/syntax/include/armv6_base_syntax.vim
index 7ec97c0..2424d60 100644
--- a/syntax/include/armv6_base_syntax.vim
+++ b/syntax/include/armv6_base_syntax.vim
@@ -13,7 +13,7 @@ exec 'syn match armv6Instr "\%(SH\?\|Q\|U[QH]\?\)\%(ADD16\|SUB16\|ADD8\|SUB8\|AS
 
 exec 'syn match armv6Instr "\%(USAD8\|USADA8\|SSAT\|SSAT16\|USAT\|USAT16\)' . armCond . '\>"'
 
-exec 'syn match armv6Instr "\%(MOVT\|MRA\|MAR\|ORN\|BFC\|BFI\|SBFX\|UBFX\)' . armCond . '\>"'
+exec 'syn match armv6Instr "\%(MOVT\|MOVW\|MRA\|MAR\|ORN\|BFC\|BFI\|SBFX\|UBFX\)' . armCond . '\>"'
 
 exec 'syn match armv6Instr "\%(PKHBT\|PKHTB\|SXTH\|SXTB16\|SXTB\|SXTAH\|SXTAB16\|SXTAB\|UXTH\|UXTB\|UXTB16\|UXTAH\|UXTAB16\|UXTAB\|RBIT\|REV\|REV16\|REVSH\|SEL\)' . armCond . '\>"'
 
@@ -22,7 +22,7 @@ exec 'syn match armv6Mul "\%(UMAAL\|SMUAD\|SMLAD\|SMLALD\|SMUSD\|SMLSD\|SMLSLD\|
 exec 'syn match armv6LDR "\%(LDREX[HBD]\)' . armCond . '\>"'
 exec 'syn match armv6STR "\%(STREX[HBD]\|CLREX\)' . armCond . '\>"'
 
-syn match armv6InstrNoCond "\%(IT\|CBN\?Z\|TBB\|TBH\|CPSID\|CPSIE\|CPS\|SETEND\|SRS\%(IA\|IB\|DA\|DB\)\|RFE\%(IA\|IB\|DA\|DB\)\)\>"
+syn match armv6InstrNoCond "\%(IT[TE]\{0,3\}\|CBN\?Z\|TBB\|TBH\|CPSID\|CPSIE\|CPS\|SETEND\|SRS\%(IA\|IB\|DA\|DB\)\|RFE\%(IA\|IB\|DA\|DB\)\)\>"
 syn keyword armv6InstrNoCond MRRC2 MCRR2
 
 exec 'syn match armv7Instr "\%(DBG\|DMB\|DSB\|ISB\|SEV\|WFE\|WFI\|YIELD\)' . armCond . '\>"'
diff --git a/test/armv7-test.s b/test/armv7-test.s
index aede69e..ff60f35 100644
--- a/test/armv7-test.s
+++ b/test/armv7-test.s
@@ -14,6 +14,7 @@ sub r14, 0b1110110-50
 0x1234567890AbCdEfG
 0xfff-0b1101+0xebbe&40%76*(0x0f)0b11/0x1f[0b110]42<>0xff|0xaa.c
 1:
+movwcs r1,r7
 and R2,r3
 bic  r3 , r4
 eor r4,r5
@@ -39,6 +40,20 @@ fdivs
 vdiv
 vsqrt
 
+it
+itt
+ittt
+itttt
+ittttt
+ite
+itet
+iteet
+iteeee
+ite
+itee
+ittee
+iteeet
+
 s30doesd32
 
 vadd.i8 d12, d16, d31