Add preliminary neon datatype suffix

Also character literals.
This commit is contained in:
ARM9 2016-02-05 16:44:33 +01:00
parent de73be2825
commit 0168ad834b
3 changed files with 16 additions and 9 deletions

View File

@ -23,9 +23,10 @@ syn region armComment start="//\|@" end="$" contains=armTodo
" syn region armComment start="^#\|//\|@" end="$" contains=armTodo
syn region armComment start="/\*" end="\*/" contains=armTodo
" Strings
syn region armString start="\"" skip=+\\"+ end="\"\|$"
syn region armString start="'" skip=+\\'+ end="'\|$"
" String literal
syn region armString start="\"" skip=+\\"+ end="\"\|[^\\]$"
" Ascii character literal
syn match armString "'\\\?[\d32-~]'\?"
so <sfile>:p:h/gas_directives.vim
so <sfile>:p:h/arm_directives.vim

View File

@ -8,7 +8,6 @@ syn match armv6Register "\<Q\%(1[0-5]\|[0-9]\)\>"
"
" ARMv6 instructions
"
exec 'syn match armv6Instr "\%(SH\?\|Q\|U[QH]\?\)\%(ADD16\|SUB16\|ADD8\|SUB8\|ASX\|SAX\)' . armCond . '\>"'
exec 'syn match armv6Instr "\%(USAD8\|USADA8\|SSAT\|SSAT16\|USAT\|USAT16\)' . armCond . '\>"'
@ -30,6 +29,7 @@ exec 'syn match armv7Instr "\%(DBG\|DMB\|DSB\|ISB\|SEV\|WFE\|WFI\|YIELD\)' . arm
"
" VFP/NEON
"
let neonDatatype = '\%(\.[isu]\?\%(8\|16\|32\|64\)\|\.f32\|\.f64\)\?'
exec 'syn match armVfpInstr "\%(FMUL\|FNMUL\|FMAC\|FNMAC\|FMSC\|FNMSC\|FADD\|FSUB\|FDIV\|FCPY\|FABS\|FNEG\|FSQRT\|FCMPE\?Z\?\|FCMPZ\|FCVTD\|FCVTS\|FUITO\|FSITO\|FTOUIZ\?\|FTOSIZ\?\|FST\|FLD\|FTO\%(SH\|SL\|UH\|UL\)\|F\%(SH\|SL\|UH\|UL\)TO\)[SD]' . armCond . '\>"'
@ -39,6 +39,5 @@ exec 'syn match armVfpInstr "\%(FSTMIA\|FSTMDB\|FLDMIA\|FLDMDB\)[SDX]' . armCond
exec 'syn match armVfpInstr "\%(VMUL\|VNMUL\|VMLA\|VMLS\|VNMLS\|VNMLA\|VADD\|VSUB\|VDIV\|VABS\|VNEG\|VSQRT\|VCMPE\?\|VCVT[TB]\?\|VMOV\|VMSR\|VMRS\|VSTR\|VSTM\%(DB\|IA\|EA\|FD\)\?\|VPUSH\|VLDR\|VLDM\%(DB\|IA\|EA\|FD\)\?\|VPOP\)' . armCond . '\>"'
exec 'syn match armNeonInstr "\%(VABA\|VABD\|VABS\|VACGE\|VACGT\|VACLE\|VACLT\|VADD\|VADDHN\|VAND\|VBIC\|VBIF\|VBIT\|VBSL\|VCEQ\|VCLE\|VCLT\|VCGE\|VCGT\|VCLE\|VCLT\|VCLS\|VCLZ\|VCNT\|VCVTR\?\|VDUP\|VERO\|VEXT\|VHADD\|VHSUB\|VLD[1234]\|VMAX\|VMIN\|VMLA\|VMLS\|VMOV\|VMOVL\|VMVN\|VQMOVN\|VQMOVUN\|VMUL\|VMLA\|VMLS\|VMULL\|VMLAL\|VMLSL\|VQABS\|VQNEG\|VORN\|VORR\|VPADD\|VPADAL\|VPMAX\|VPMIN\|VQADD\|VQDMLAL\|VQDMLSL\|VQDMULL\|VQDMUL\|VQDMULH\|VQRDMULH\|VQRSHL\|VQRSHR\|VRSHL\|VQSHRUN\|VQSHL\|VQSHR\|VQSUB\|VRADDH\|VRADDHN\|VRSUBHN\|VRECPE\|VRECPS\|VRSQRTE\|VRSQRTS\|VQSHLU\|VSHLL\|VREV\|VRHADD\|VRSHR\|VRSRA\|VRSHRN\|VRSUBH\|VSHL\|VSHR\|VQSHRN\|VQRSHRN\|VQRSHRUN\|VSLI\|VSRA\|VSRI\|VST[1234]\|VADDL\|VADDW\|VSUBL\|VSUBW\|VSUBH\|VSUBHN\|VSWP\|VTBL\|VTBX\|VTRN\|VTST\|VUZP\|VZIP\)' . armCond . '\>"'
exec 'syn match armNeonInstr "\%(VABA\|VABD\|VABS\|VACGE\|VACGT\|VACLE\|VACLT\|VADD\|VADDHN\|VAND\|VBIC\|VBIF\|VBIT\|VBSL\|VCEQ\|VCLE\|VCLT\|VCGE\|VCGT\|VCLS\|VCLZ\|VCNT\|VCVTR\?\|VDUP\|VEOR\|VEXT\|VHADD\|VHSUB\|VLD[1234]\|VMAX\|VMIN\|VMLA\|VMLS\|VMOV\|VMOVL\|VMVN\|VQMOVN\|VQMOVUN\|VMUL\|VMLA\|VMLS\|VMULL\|VMLAL\|VMLSL\|VQABS\|VQNEG\|VORN\|VORR\|VPADD\|VPADAL\|VPMAX\|VPMIN\|VQADD\|VQDMLAL\|VQDMLSL\|VQDMULL\|VQDMUL\|VQDMULH\|VQRDMULH\|VQRSHL\|VQRSHR\|VRSHL\|VQSHRUN\|VQSHL\|VQSHR\|VQSUB\|VRADDH\|VRADDHN\|VRSUBHN\|VRECPE\|VRECPS\|VRSQRTE\|VRSQRTS\|VQSHLU\|VSHLL\|VREV\|VRHADD\|VRSHR\|VRSRA\|VRSHRN\|VRSUBH\|VSHL\|VSHR\|VQSHRN\|VQRSHRN\|VQRSHRUN\|VSLI\|VSRA\|VSRI\|VST[1234]\|VADDL\|VADDW\|VSUBL\|VSUBW\|VSUBH\|VSUBHN\|VSWP\|VTBL\|VTBX\|VTRN\|VTST\|VUZP\|VZIP\)' . armCond . neonDatatype . '\>"'

View File

@ -6,6 +6,7 @@ _bar:
.L09:
.1337f:
ab.b: b blabl
1234:
adc r0, r1
add R1, R2
@ -48,24 +49,30 @@ ittttt
ite
itet
iteet
iteee
iteeee
ite
itee
ittee
ittte
itttte
itttee
iteeet
s30doesd32
vadd.i8 d12, d16, d31
vmull.s32 q2, d5, D6
vmov.f64 vmov.f32 vmov
vcle. vceq vclt.f vcge.8 vtst.16 vcle.f32
.float .01, 3.14159
{14,140-402(0x1b-0b1101+.0#0.0#.0.[123]0xffff%#0x34%$0xf$#0b111#$0b11b{ldr#0b11-ldr1)}
@ illegal
1.0f 0.f .1f
vmul Q15, Q16, d31, s31, s32, d32
vmull q01, q09, q14, q16
pop {s3-s32}
vmulk Q15, Q16, d31, s31, s32, d32
vmull2 q01, q09, q14, q16
ppop {s3-s32}
vadd#1234?ldr$12?str12
@ vim:ft=arm