Zander671/arm-syntax-vim
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fixed bug that caused some armv4 instructions to not highlight

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This commit is contained in:
ARM9
2015-04-03 16:32:27 +02:00
parent e457b8cd10
commit c5eaf804fb
3 changed files with 22 additions and 19 deletions
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2
syntax/armv5.vim
View File

@ -18,7 +18,7 @@ if version >= 508 || !exists("did_armv5_syntax_inits")
command -nargs=+ HiLink hi def link <args>
endif
so <sfile>:p:h/include/arm_base_syntax.vim
so <sfile>:p:h/include/armv5_base_syntax.vim
HiLink armv4Instr armv5Instructions
HiLink armv5InstrCond armv5Instructions

19
syntax/include/arm_base_syntax.vim
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@ -46,29 +46,12 @@ exec 'syn match armv4Instr "\%(ADC\|ADD\|AND\|BIC\|EOR\|MLA\|MOV\|MUL\|MVN\|NEG\
exec 'syn match armv4InstrCond "\%(B\|BL\|BX\|CDP\|CMN\|CMP\|LDC\|MCR\|MRC\|MRS\|MSR\|STC\|SWI\|TEQ\|TST\)' . armCond . '\>"'
syn match armv4InstrNoCond "\%(ASR\|LSL\|LSR\|NOP\|POP\|PUSH\|ROR\|RRX\)\>"
syn match armv4InstrNoCond "\%(ASR\|LSL\|LSR\|NOP\|POP\|PUSH\|ROR\|RRX\)\>"
exec 'syn match armv4LDR "\%(LDR\)' . armCond . '\%(B\?T\?\|H\|S[BH]\)\?\>"'
exec 'syn match armv4STR "\%(STR\)' . armCond . '\%(B\?T\?\|H\)\?\>"'
exec 'syn match armv4Stack "\%(LDM\|STM\)' . armCond . '\%([ID][BA]\|[EF][DA]\)\>"'
exec 'syn match armv4SWP "SWP' . armCond . 'B\?\>"'
"
" ARMv5 instructions
"
exec 'syn match armv5InstrCond "\%(BLX\|CLZ\|MCRR\|MRRC\|QADD\|QSUB\|QDADD\|QDSUB\)' . armCond . '\>"'
HiLink armv4InstrCond armv5InstrCond
syn match armv5InstrNoCond "\%(BKPT\|CDP2\|LDC2\|MCR2\|MRC2\|PLD\|STC2\)\>"
HiLink armv4InstrNoCond armv5InstrNoCond
exec 'syn match armv5Mul "\%(SMLA\|SMLAL\|SMLAW\|SMUL\|SMULW\)[BT][BT]' . armCond . '\>"'
exec 'syn match armv5LDR "\%(LDR\)' . armCond . 'D\>"'
exec 'syn match armv5STR "\%(STR\)' . armCond . 'D\>"'
HiLink armv4LDR armv5LDR
HiLink armv4STR armv5STR
"syn match armRelative "@R[0-7]\|@a\s*+\s*dptr\|@[ab]"

20
syntax/include/armv5_base_syntax.vim Normal file
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@ -0,0 +1,20 @@
so <sfile>:p:h/arm_base_syntax.vim
"
" ARMv5 instructions
"
exec 'syn match armv5InstrCond "\%(BLX\|CLZ\|MCRR\|MRRC\|QADD\|QSUB\|QDADD\|QDSUB\)' . armCond . '\>"'
HiLink armv4InstrCond armv5InstrCond
syn match armv5InstrNoCond "\%(BKPT\|CDP2\|LDC2\|MCR2\|MRC2\|PLD\|STC2\)\>"
HiLink armv4InstrNoCond armv5InstrNoCond
exec 'syn match armv5Mul "\%(SMLA\|SMLAL\|SMLAW\|SMUL\|SMULW\)[BT][BT]' . armCond . '\>"'
exec 'syn match armv5LDR "\%(LDR\)' . armCond . 'D\>"'
exec 'syn match armv5STR "\%(STR\)' . armCond . 'D\>"'
HiLink armv4LDR armv5LDR
HiLink armv4STR armv5STR